This invention relates generally to the manufacture of printed wiring boards and more specifically to the manufacture of multilayered printed wiring boards using generally additive processes.
Ongoing integration and miniaturization of electronic circuit components is challenging the limits of printed circuit board technology. Printed circuit boards or printed wiring boards (PWB), as they are more accurately termed, play several indispensable roles in electronic devices of all kinds. First, the individual electrical components, such as specially packaged integrated circuits, resistors, etc., are mounted or carried on the surface of the flat usually sturdy card-like board. Thus, the PWB serves as a unitary mechanical support for the components. Secondly, using chemically etched or plated conductor patterns on the surface of the board, the PWB forms the desired electrical interconnections between the components. In addition, the PWB often includes metal areas serving as heat sinks for high power or thermally sensitive components. As the use of integrated circuits has grown, the higher density of interconnections has necessitated double-sided PWB's in which additional interconnections are made employing conductor patterns on the other side of the board. This trend has been extended to boards of many layers of interconnections termed multilayer PWB's. Connections from layer to layer are typically made by plated through holes.
Conductor patterns are typically formed by photoetching a copper foil clad epoxy fiberglass substrate. A photoresist layer is applied to the copper foil and patterned by exposure to ultraviolet light through a stencil-like film artwork mask. Areas exposed on the photoresist are polymerized. The unpolymerized areas are removed by a chemical solution leaving areas of copper, the desired conductor pattern, underneath the protective barrier of the remaining polymerized photoresist. The exposed copper is then etched away and the remaining photoresist is chemically removed to expose the resulting conductor pattern. There are, of course, many popular variations on this procedure, for example, pattern plating where electroplated copper is added through a patterned resist to form the conductors. However, all of those which require etching of the conductor patterns undercut the conductor pattern to varying degrees because only the top surface is protected from the etchant. Undercutting becomes increasingly troublesome when extremely fine conductor lines are required.
Along with increased circuit integration, surface mount technology (SMT) has greatly accelerated the densification of electronic circuitry offering a reduction in space requirements of up to 70%. Surface mount devices (SMD) are applied directly to the surface of the PWB and soldered using vapor phase, solder reflow or other techniques. Registration of surface mounted integrated circuits having many terminals on fine pitch requires extremely fine resolution for the PWB conductors.
At the same time, electroless plating technology has been rapidly improving. In this system, widely used by the Japanese manufacturers on paper laminate substrates, conductor paths are chemically grown by metal deposition in large plating baths. Improved bath formulations and bath operation systems have recently encouraged the use of electroless plating techniques outside Japan. In one process a catalytic substrate is coated with a photoresist. After patterning the resist, the holes through the resist are filled up with metal using electroless plating. Since conductors are produced by the addition of metal rather than by subtraction, i.e., etching, the process is called "additive". Conductor paths can be produced in this manner to a desired thickness. Generally, electroless plating techniques reduce or eliminate the effects of undercutting and produce a straight-sided conductor of virgin metal. However, they have required the use of exotic catalytic materials to promote copper deposition and adhesion.
SMD circuitry, however, has become so dense that multilayer PWB's have become the focus of attention and several competing technologies are evolving. Simple stacks of fiberglass epoxy PWB's can be bonded together and interconnections made by drilled plated through holes. Cofired ceramic technology uses another stacking technique. Potted wire matrices have also been proposed. All of these systems have numerous drawbacks. For example, if layers 2 and 3 in a four-layered PWB require an interlayer connection, a through hole has to be made through the entire structure thus consuming "real estate" on layers 1 and 4 which could otherwise be put to use. So-called blind vias with buried interconnections between two or more internal layers are not well accommodated by existing techniques.